Semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. In contrast to volatile memory devices, nonvolatile memory devices, such as flash memory devices, retain stored data even when power is removed. Therefore, nonvolatile memory devices, such as flash memory devices, are widely used in memory cards and in electronic devices. Due to rapidly growing digital information technology, there are demands to continuingly increase the memory density of the flash memory devices while maintaining, if not reducing, the size of the devices.
Three-dimensional (3D)-NAND flash memory devices have been investigated for increasing the memory density. The 3D-NAND architecture includes a stack of memory cells having a plurality of charge storage structures (e.g., floating gates, charge traps or the like), a stack of alternating control gates and dielectric materials, and charge blocking materials disposed between the charge storage structures (mostly referred to by example as floating gates hereinafter) and the adjacent control gates. An oxide material, such as silicon oxide, is conventionally used as the dielectric material. The charge blocking material may be an inter-poly dielectric (IPD) material, such as oxide-nitride-oxide (ONO) material.
FIG. 1 shows a semiconductor structure 100 that may be further processed to form a 3D-NAND flash memory device. The semiconductor structure 100 includes a stack 110 of alternating control gates 108 and dielectric materials 105 over a material 103 to be used as control gate of a select device, such as a select gate source (SGS) or a select gate drain (SGD), a plurality of floating gates 400, a charge blocking material (411, 412, 413) positioned between the floating gates 400 and adjacent control gates 108, and a channel material 500 extending through the stack 110, the control gate material 103, a dielectric material 102, and a portion of a source 101. The source 101 could be formed in and/or on a substrate (not shown), such as a semiconductor substrate comprising monocrystalline silicon. Optionally, the semiconductor structure 100 may include an etch stop material 104. Although not depicted here, in other embodiments, the depicted material 101 may form or be part of a bit line (e.g., instead of a source). The control gates 108 each has a height of L1. The floating gates 400 each has a height of L2. Due to the presence of the charge blocking material (411, 412, 413) around the discrete floating gate 400, the height L2 of each discrete floating gate 400 is approximately half the height L1 of an adjacent control gate. For example, the height of the floating gate in the direction of current flow (e.g., in a pillar of a string of the memory cells) may be approximately 15 nm compared to the height of an adjacent control gate, which is approximately 30 nm. In addition, the floating gate is not aligned with the adjacent control gate.
During use and operation, a charge may get trapped on portions of the IPD material, such as on portions of the IPD material that are horizontally disposed between a floating gate and adjacent dielectric material. When the IPD material is an ONO material, the charge may get trapped in the horizontal nitride portions of the IPD material that are not between the control gates and the floating gates. Trapped charge can migrate along the IPD material, such as through program, erase or temperature cycling. The presence of the IPD material creates a direct path for programming/erasing into the nitride material of the IPD material and degrades cell program-erase cycling. Such charge trapping or movement can alter the threshold voltage (Vt) of the memory cells or degrade incremental step pulse programming (ISPP) relative to memory cells that do not have such charge trapping in the nitride. Charge trap jeopardizes the controllability of the channel characteristics and the reliability of the 3D-NAND flash memory device.
To minimize charge trap in the horizontal IPD portions, it is desirable to reduce the amount of the horizontal IPD portions, such as by increasing the height of a floating gate relative to the height of an adjacent control gate. In addition to reducing the undesirable charge trap, increasing the height of floating gate in the direction of current flow through the channel may offer a higher degree of channel conductance modulation (e.g., a higher on/off ratio), a reduced cell noise (e.g., a larger floating gate), and a reliability gain. The attempts to increase the height of floating gates to about the same as that of adjacent control gates require the addition of numerous deposition/dry/wet etch steps, resulting in a complex and rather costly fabrication process. Furthermore, these additional deposition/dry/wet etch steps often associate with an undesirable increase in the critical dimension.
Therefore, it would be beneficial to have a fabrication process for forming the floating gates having a height approximately the same as the height of adjacent control gates that utilizes relatively few additional acts and without jeopardizing other properties and performances of the fabricated structure.